In receivers of this type, the PLL circuit is generally the source of phase noise which gets added to the signal S.sub.FI (t) and which causes a deterioration in the quality of the information transmitted. Thus, excessive phase noise increases the error rate in the demodulated signal especially in transmission devices which use QPSK modulation (Quadriphase shift keying) or modulation of the QAM type (Quadrature amplitude modulation).
FIG. 1 represents diagrammatically a phase-locked loop circuit used in known receivers. The total phase noise generated by such a circuit results from the contribution from its constituent elements such as a reference oscillator, a voltage-controlled oscillator VCO, a phase detector, a filtering operational amplifier and sometimes a divider. Generally, the VCO is regarded as constituting the major source of phase noise. Thus, this element includes a variable-capacitance diode (or varactor) having an equivalent resistance which causes a noise voltage producing modulation of the voltage across the terminals of the said varactor. This noise prevails in the VCO over a wide range of frequencies of oscillation.
The objective of the invention is to eliminate the phase noise generated by the PLL circuit in digital receivers.
According to the invention, the digital receiver includes a phase noise digital correction stage intended for tapping off the noise signal .phi..sub.n (t) generated by the PLL circuit in the mixer stage and for compensating the said noise .phi..sub.n (t) in the demodulation stage.
By virtue of the noise correction stage, the demodulated signal is error-free thus enabling the quality of the information transmitted to be improved.